Patents
U.S. Patents
1) #4,865,375, Israel Bienglass and John Borland, Method Of Constructing Lightly Doped Drain (LDD) Integrated Circuit Structure, Dec. 4, 1990. Patent #1
2) #5,501,993, John O. Borland, Method Of Constructing CMOS Vertically Modulated Wells (VMW) By Clustered MeV BILLI (Buried Implanted Layer for Lateral Isolation) Implantation Mar. 26, 1996. Patent #2
3) #5,814,866, John O. Borland, Semiconductor Device Having At Least One Field Oxide Area And CMOS Vertically Modulated Wells (VMW) With A Buried Implanted Layer for Lateral Isolation Having A First Portion Below A Well, A Second Portion Forming Another, Adjacent Well, Sept. 29, 1998. Patent #3
4) #5,821,589, John O. Borland, Method For CMOS Latch-up Improvement By MeV BILLI Plus Buried Layer Structure, Oct. 13, 1998. Patent #4
5) #6,187,643, John O. Borland, Simplified Semiconductor Device Manufacturing Using Low Energy High Tilt Angle And High Energy Post-Gate Ion Implantation (PoGI), Feb.13,2001. Patent #5
6) #7,259,036, John O. Borland, John Hautla, Wesley Skinner and Martin Tabat, Methods of Forming Doped and Un-doped Strained Semiconductor Materials and Semiconductor Films By Gas-Cluster-Ion-Beam Irradiation and Materials and Film Products, Aug. 21, 2007. Patent#6