J.O.B. Technologies

1) H. Saito, J. O. Borland, H. Asahi, H. Nagai and K. Nawata, “Hillock Defects In InGaAs/InP Multilayers Grown By MBE”, Journal of Crystal Growth, vol.64, p.521, 1983.
2) J.O. Borland, “Activation Of The Intrinsic Gettering Mechanism By The Growth Of Oxygen Related Precipitates In Cz-Grown Silicon Wafers”, Defects In Silicon, the Electrochemical Society, PV 83-9, p.194, 1983.
3) J.O. Borland, “The Homogenation Of Micro-Defects In The Bulk Of Silicon Wafers By A Three-Step Heat Treatment”, Defects In Silicon, the Electrochemical Society, PV 83-9, p.236, 1983.
4) J.O. Borland, M. Kuo, J. Shibley, B. Roberts, R. Schindler and T. Dalrymple, “An Intrinsic Gettering Process To Improve Minority Carrier Lifetimes In MOS And Bipolar Silicon Epitaxial Technology”, Semiconductor Processing, ASTM STP 850, American Society for Testing and Materials, p.49, 1984.
5) J.O. Borland, “The Effects Of Wafer Thermal History On The 450^oC Thermal Donor Formation In Cz-Grown P(100) Silicon”, Semiconductor Processing, ASTM STP 850, American Society for Testing and Materials, p.201, 1984.
6) J.O. Borland, M. Kuo, J. Shibley, B. Roberts, R. Schindler and T. Dalrymple, “Influence Of Epi-Substrate Point Defect Properties On Getter Enhanced Silicon Epitaxial Processing For Advanced CMOS And Bipolar Technologies”, VLSI Science and Technology 1984, the Electrochemical Society, PV 84-7, p.93, 1984.
7) J.O. Borland, M. Kuo, J. Shibley, B. Roberts, R. Schindler and T. Dalrymple, “Influence Of Epi-Substrate Point Defect Properties On Getter Enhanced Silicon Epitaxial Processing For Advanced CMOS And Bipolar Technologies”, Chemical Vapor Deposition 1984, the Electrochemical Society, PV 84-6, p.324, 1984.
8) J.O. Borland and T. Deacon, “Advanced CMOS Epitaxial Processing For Latch-up Hardening And Improved Epilayer Quality”, Solid State Technology, vol.27, no.8, p.123, Aug. 1984.
9) J.O. Borland and R.S. Singh, “Improved CMOS Device Performance Through Silicon Epitaxial Intrinsic Gettering Techniques”, The 16th (1984 International) Conference on Solid State Devices and Materials, the Japan Society of Applied Physics, p.487, Aug. 1984.
10) J.O. Borland, “Influence Of Micro-Defect Morphology On Intrinsic Gettering Effectiveness And Durability In CMOS Epitaxial Processing”, Impurity Diffusion and Gettering in Silicon, the Materials Research Society Symposia Proceedings, vol.36, p.269, 1985.
11) J.O. Borland and R.S. Singh, “Improved P-Well CMOS Latch-up Immunity And Device Performance Through Intrinsic Gettering Techniques”, VLSI Science and Technology 1985, the Electrochemical Society, PV 85-5, p.77, 1985.
12) K.H. Choi, J.O. Borland and S.K. Hahn, “Improved N-Well CMOS Latch-up Immunity Through The Optimization Of Epilayer Thickness And Resistivity”, VLSI Science and Technology 1985, the Electrochemical Society, PV 85-5, p.88, 1985.
13) S.K. Hahn, J.O. Borland and D. Wong, “Effects Of N-type Substrate On Epilayer Quality For Twin Tub CMOS Technology”, VLSI Science and Technology 1985, the Electrochemical Society, PV 85-5, p.96, 1985.
14) R.E. Logar and J.O. Borland, “Silicon Epitaxial Processing Techniques For Ultra-Low Defect Densities”, Solid State Technology, vol.28, no.6, p.133, June 1985.
15) J.O. Borland and C.I. Drowley, “Advanced Dielectric Isolation Through Selective Epitaxial Growth Techniques”, Solid State Technology, vol.28, no.8, p.141, Aug. 1985.
16) J.O. Borland, “Advanced Epitaxial Processing For Submicron Device Technology”, Presented at Semiconductor International Korea, March 1986, Applied Materials, Inc. Technical report HT-030, 1986.
17) T. Tuomi, S.K. Hahn, M. Tilli, C.C.D. Wong and J.O. Borland, “Oxygen Precipitation Studies For N-type And Epitaxial Silicon Substrates During Simulated CMOS Cycles By Synchrotron Section Topography”, Materials Issues In Silicon Integrated Circuit Processing, Materials Research Society Symposia Proceedings, vol.71, p.47, 1986.
18) C.C.D. Wong, J.O. Borland and S.K. Hahn, Invited Paper “Effects Of Gettering On Epi Quality For CMOS Technology”, Emerging Semiconductor Technology, ASTM STP 960, American Society for Testing and Materials, p.51, 1987.
19) J.O. Borland, D.N. Schmidt and A.R. Stivers, “Low Temperature Low Pressure Silicon Epitaxial Growth And Its Application To Advanced Dielectric Isolation Technology”, The 18th (1986 International) Conference on Solid State Devices and Materials, SSDM-86, the Japan Society of Applied Physics, p.53, Aug. 1986.
20) J.O. Borland and D.N. Schmidt, “High Quality Low Temperature, Low Pressure CVD Epitaxial Silicon”, Technical Proceedings Semicon/East 1986, p.150, Sept. 1986.
21) J.O. Borland, “Advanced CMOS Epitaxial Technology”, Semiconductor and Integrated Circuit Technology, Chinese Institute of Electronics and the continuing Education in Engineering University Extension University of California at Berkeley, p.177, Oct. 1986.
22) J.O. Borland, Invited Paper “Intrinsic Gettering In (CMOS) Epitaxial Silicon”, ”, Semiconductor and Integrated Circuit Technology, Chinese Institute of Electronics and the continuing Education in Engineering University Extension University of California at Berkeley, p.197, Oct. 1986.
23) J.O. Borland, “Intrinsic Gettering For CMOS Bulk And Epi Technology”, Gettering And Defect Engineering In The Semiconductor Technology, Institute of Semiconductor Physics Academy of Sciences of the GDR, p.360, Oct. 1987.
24) J. Borland, T. Thompson, V. Tagle and W. Benzing, “Boron, Arsenic And Phosphorus Dopant Incorporation During Low Temperature Low Pressure Silicon Epitaxial Growth”, Chemical Vapor Deposition 1987, the Electrochemical Society, PV 87-8, p.275, 1987.
25) J.O. Borland, Invited Paper “Historical Review Of SEG And Future Trends In Silicon Epi Technology”, Chemical Vapor Deposition 1987, the Electrochemical Society, PV 87-8, p.307, 1987.
26) A.R. Stivers, C.H. Ting and J.O. Borland, “Growth Condition Dependence of SEG Planarity And Electrical Characteristics”, Chemical Vapor Deposition 1987, the Electrochemical Society, PV 87-8, p.389, 1987.
27) S.T. Liu, L. Chan and J.O. Borland, “Reaction Kinetics Of SiO₂/Si (100) Interface In H₂ Ambient In A Reduced Pressure Epitaxial Reactor”, Chemical Vapor Deposition 1987, the Electrochemical Society, PV 87-8, p.428, 1987.
28) J.O. Borland, Invited Paper “Novel Device Structures By Selective Epitaxial Growth”, Technical Digest International Electron Device Meeting 1987, Electron Device Society of IEEE, IEDM-87, section 2.1, p.12, Dec. 1987.
29) J. Manoliu and J.O. Borland, “A Submicron Dual Buried Layer Twin Well CMOS SEG Process”, Technical Digest International Electron Device Meeting 1987, Electron Device Society of IEEE, IEDM-87, section 2.3, p.20, Dec. 1987.
30) J. Borland, R. Wise, M. Gangani, S. Fong, Y. Matsumoto and Y. Oka, “Silicon Epitaxial Growth For Advanced Device Structures”, Solid State Technology, vol.31, no.1, p.111, Jan. 1988.
31) M. Goulding and J. Borland, “Low vs High Temperature Epitaxial Growth”, Semiconductor International, p.90, May 1988.
32) J. Borland, “New Device Structures By Advanced Silicon Epitaxial Growth Techniques”, Technical Proceedings Semicon/Japan 1988, SEMI, p.80, Nov. 1988.
33) J.O. Borland, “Borland’s Overview Of The Latest In Intrinsic Gettering: Part I”, Semiconductor International, p.144, Apr. 1989.
34) J.O. Borland, “Borland’s Overview Of The Latest In Intrinsic Gettering: Part II”, Semiconductor International, p.154, May 1989.
35) C.S. Wei, V. Murali, M.L.A. Dass, D. Fraser and J. Borland, “The Use Of Selective Silicide Plugs For Submicron Contact Fill”, the IEEE 1989 VLSI Multilevel Interconnect Conference, VMIC-89, p.136, June 1989.
36) J.O. Borland and J.C. Hann, “BiCMOS Epi Processing For Buried Layer Autodoping And Pattern Control”, ULSI Science and Technology 1989, the Electrochemical Society, PV 89-9, p.254, 1989.
37) V.J. Silverstri, K. Nummy, P. Ronsheim, R. Bendernagel, D. Kerr, V.T. Phan, J.O. Borland and J. Hann, “ULSI Quality Silicon Epitaxial Growth At 850^oC”, ULSI Science and Technology 1989, the Electrochemical Society, PV 89-9, p.266, 1989.
38) C.S. Wei, V. Murali, D. Fraser and J. Borland, “The Use Of Selective Silicon Or Silicide Plugs For Submicron Contact Fill”, ULSI Science and Technology 1989, the Electrochemical Society, PV 89-9, p.637, 1989.
39) D.M. Boisvert, J.D. Plummer and J.O. Borland, “Dielectric Isolation Of Silicon Through SEG/ELO In Trenches”, High Voltage And Smart Power ICs, the Electrochemical Society, PV 89-15, p.334, 1989.
40) J.O. Borland, Invited Paper “Recent Advances In Silicon Epitaxial Growth For Advanced Device Structures”, the 1989 International Conference on VLSI and CAD, Korea Institute of Telematics and Electronics and IEEE, ICVC-89, p.557, Oct. 1989.
41) M. El-Diwany, J. Borland, J. Chen, S. Hu, P. v.Wijnen, C. Vorst, V. Akylas, M. Brassington and R. Razouk, “An Advanced BiCMOS Process Utilizing Ultra-Thin Silicon Epitaxy Over Arsenic Buried Layers”, 1989 International Electron Device Meeting, IEEE IEDM-89, section 9.7, p.245, Dec. 1989.
42) J. Borland and I. Bienglass, “Selective Silicon Deposition For The Megabit Age”, Solid State Technology, vol.33, no.1, p.73, Jan. 1990.
43) J. Borland, “Epitaxial Growth Of Silicon: Selective And Non-Selective”, Proceedings of the Brazilian Microelectronics School, p.366, Mar. 1990.
44) M. Arst, J. Chen, K. Ritz, J. Borland and J. Hann, “A Novel Simultaneous Single/Poly Deposition (SSPD) Technique For New And Scaled-Down Device Structures”, Semiconductor Silicon 1990, the Electrochemical Society, PV 90-7, p.794, 1990.
45) M. Arst, K. Ritz, S. Redkar, J. Borland and J. Hann, “Surface Planarity And Microstructure Of Low Temperature Silicon SEG And ELO”, Journal of Materials Research, the Materials Research Society, vol.6, no.4, p.784, April 1991.
46) I. Rahat, J. Shappir, D. Fraser, J. Wei, J. Borland and I. Beinglass, “Reducing the Temperature of conventional Silicon Epitaxy for Selective Poly-Epi Growth”, Journal of the Electrochemical Society, vol.138, no.8, p.2370, Aug. 1991.
47) J.O. Borland, “The Current Status of Commercial Low Temperature Silicon Epitaxy”, the Journal of the Minerals, Metals and Materials Society, p.23, Oct. 1991.
48) J.O. Borland, “Wet and Dry Ex-situ/In-situ Cleaning for Control of Interface Impurities and Microstructure of Low Temperature Silicon Deposition”, Symposium on Advanced Science and Technology of Silicon Materials, Japan Society for the Promotion of Science, p.306, Nov. 1991.
49) J.O. Borland, Invited Paper “Silicon Epitaxial Equipment and Processing Advances for Bipolar Base Technology”, 1992 Bipolar Circuits and Technology Meeting, IEEE, section 1.1, p.16, Oct. 1992.
50) J.O. Borland, C. Riggi and F. Brocious, “Silicon Surface Cleaning For Low Temperature Epitaxial Growth”, Surface Chemical Cleaning and Passivation for Semiconductor Processing, the Materials Research Society Symposia Proceedings, vol.315, p.71, 1993.
51)  J. Borland, D. Carlson, C. Riggi, B. Gong, L. Florendo, C. Pohl and P. Hey, “Characterization of a Single Wafer Multi-Chamber Clustered Epi System at Reduced Pressure”, Chemical Vapor Deposition 1993, the Electrochemical Society, PV 93-2, p.147, 1993.
52) J.B. Price, J.O. Borland and S. Selbrede, “Properties of Chemical-Vapor-Deposited Titanium Nitride”, Thin Solid Films, vol.236, p.311, 1993.
53) J.M. deLarios, J.O. Borland, S. Hatada and I. Tamatani, “Selective Etching of Native Oxide Using Vapor HF Processing”, Extended Abstracts of the 1993 International Conference on Solid State Devices and Materials, the Japan Society of Applied Physics, SSDM-93, p.140, Aug. 1993.
54) J.M. deLarios and J.O. Borland, “Selective Etching of Native Oxide Using Vapor HF Processing”, Cleaning Technology, the Electrochemical Society, PV 93-?, p. ???, Oct. 1993.
55) J.O. Borland and R. Koelsch, “Cost-Competitive Processing Using High Energy Ion Implantation”, Semiconductor International, p.90, Oct. 1993.
56) J.O. Borland and R. Koelsch, “MeV Implantation Technology: Next-Generation Manufacturing With Current-Generation Equipment”, Solid State Technology, p.90, Dec. 1993.
57) M. Gardner, D. Wristers, J. Fulford and J. Borland, “Hydrogen Denudation For Enhanced Thin Oxide Quality, Device Performance and Potential Epitaxial Elimination”, 1994 Symposium on VLSI Technology Digest of Technical Papers, p.8B.4, June 1994.
58) J.O. Borland, “Applications of MeV Ion Implantation Technology”, Ion Implantation Technology-94, p.950, June 1994.
59) J.O. Borland, Invited Paper “Applications of MeV Ion Implantation in Semiconductor Device Manufacturing”, Beam-Solid Interactions for Materials Synthesis and Characterization, the Materials Research Society Symposium Proceedings, vol.354, p.123.
60) J.O. Borland, Invited Paper “Applications of MeV Ion Implantation in Semiconductor Device Manufacturing”, Semicon/Korea 95 Process Technology, p.107, Jan. 1995.
61) S.T. Picraux, E. Chason, J.M. Poate, J.O. Borland, M.I. Current, T.Diaz deLaRubia, D.J. Eaglesham, O.W. Holland, M.E. Law, C.W. Magee, J.W. Mayer, J. Melngailis and A.F. Tasch, “Energetic Ion Beams In Semiconductor Processing: Summary of a DOE Panel Study”, the Materials Research Society Symposium Proceedings, vol.396, p.859, 1996.
62) J.O. Borland and T.E. Seidel, “Epi Replacement In Manufacturing Using MeV Implantation”, Solid State Technology, p.89, June 1996.
63) J.O. Borland, “Current & Emerging Production Applications/Trends of MeV Technology”, Ion Implantation Technology-96, June 1996.
64) J.O. Borland, D. Wristers, J. Walker and D. Daniel, “Epi Avoidance For CMOS Logic Devices Using MeV Implantation”, Ion Implantation Technology-96, June 1996.
65) W.J. Lee, N. Tokoro, H.T. Cho and J.O. Borland, “Thick PhotoResist Outgassing During MeV Implantation (Mechanism & Impact on Production)”, Ion Implantation Technology-96, June 1996.
66) J.O. Borland, “Substrate Defect Engineering with MeV Implant Technology”, Defect Engineering in Submicron Process Technologies, Semicon/Southwest 96, p.95, Oct. 1996.
67) J.O. Borland, “Emerging MeV Twin & Triple Wells”, European Semiconductor, April 1997.
68) J. Borland and J. Kawski, “Triple Well Applications Profit From MeV Implant Technology”, Semiconductor International, April 1998, p.67.
69) J.K. Kim, J. Borland and H.T. Cho, “LOCOS-vs-Shallow Trench Isolation Latch-up Characterization Using MeV Implantation For Well Formation Down To 0.18um Design Rules”, the 12^th International Conference on Ion Implantation Technology “98 June 22-26, 1998 in Kyoto, Japan, p.67.
70) M. Teague, S. Johns and J. Borland, “Epi Replacement And Up To 30% Process Simplification In A CMOS Foundry Environment Using The BILLI Structure”, the 12^th International Conference on Ion Implantation Technology “98 June 22-26, 1998 in Kyoto, Japan, p. 63.
71) J. Borland and C. Galewski, “Using Dopant Activation Of Implanted Wafers For Low Temperature (400-600C) Measurement In CVD Equipment Design”, the 12^th International Conference on Ion Implantation Technology “98 June 22-26, 1998 in Kyoto, Japan, p. 1211.
72)  J. Borland, “CMOS Isolation Latch-up Characterization, Implant Defect Control And Well Formation Options Using MeV Implantation”, the 12^th International Conference on Ion Implantation Technology “98 June 22-26, 1998 in Kyoto, Japan.
73) J. Borland, “Improved Device Scaling & Process Simplification Through Advanced Ion Implantation Techniques”, the Electrochemical Society, ECS PV2001-2, p.273.
74) J. Borland, “Advanced Ion Implantation Brings New Changes”, Semiconductor International, vol. 24, no.4, April 2001, p.70.
75) J. Borland, “Low Temperature Shallow Junction Formation For 70nm Technology Node And Beyond”, invited talk Spring MRS 2002 Meeting, April 2, 2002.
76) J. Borland, T. Matsuda and K. Sakamoto, “Shallow And Abrupt Junction Formation: Paradigm Shift at 65-70nm”, Solid State Technology, p. 83, June 2002.
77) S. Felch, J. Borland, Z. Fang, J. Koo, A. Fiorey, H. Grossman, K. Jones, C. Linfords, P. Borden, “Extending Ion Implantation Shallow Junction Formation To 50nm Node Using Low Temperature Processing”, IIT-2002, Sept. 2002.
78) J. Borland, “Low Temperature Ion Implanted Dopant Activation: A Review” invited paper at the International Workshop on Junction Technology (IWJT) Dec. 2002 in Tokyo, Japan.
79) J. Borland, H. Iwai, W. Maszara and H. Wang, “Extending the Life of Planar CMOS with Multi-Gate CMOS Devices”, vol. 46, no.3, p.26, March 2003.
80) J. Borland, H. Iwai, W. Maszara and H. Wang, “Extending Planar Single-Gate CMOS and Accelerating the Understanding of Double-Gate CMOS Transistors”, the Electrochemical Society, PV 2003-06, p. 330, April 2003.
81) J. Borland and V. Moroz, “Implantation And Annealing Options For 65nm Node SDE Formation”, Semiconductor International, vol. 26, no. 4, April 2003, p.72.
82) J. Borland, V. Moroz, H. Wang, W. Maszara and H. Iwai, “Lateral Graded S/D Engineering By High Tilt Implantation & Diffusion-less Activation: Extending The Scalability Of Single-Gate, Double-Gate And Multi-Gate CMOS Devices”, Solid State Technology, June 2003, p.52.
83) J. Borland, “USJ Formation & Characterization For 65nm Node And Beyond”, the International Workshop on Junction Technology (IWJT), p.8, March 2004, Shanghai, China.
84) R. Hillard, J. Borland and W. Ye, “Accurate Determination Of Ultra-Shallow Junction Sheet Resistance With A Non-Penetrating Four Point Probe”, the International Workshop on Junction Technology (IWJT),p. 98, Mar. 2004, Shanghai, China.
85) J. Hatula, J. Borland, M. Tabat and W. Skinner, “Infusion Doping For USJ Formation”, the International Workshop on Junction Technology (IWJT), p.50, Mar. 2004, Shanghai, China.
86) R. Hillard, R. Mazur, W. Alexander, C.W. Ye, M. Benjamin and J. Borland, “Measurements of Ultra-Shallow Junction (USJ) Sheet Resistance With A Non-Penetrating Four Point Probe”, MRS Spring meeting, April 2004, Material Research Society Symposium Proceedings, vol. 810, p. 463.
87) J. Borland, J. Hatula, T. Tetella, M. Tabat, M. Gwinn and W. Skinner, “USJ and Strained-Si Formation Using Infusion Doping and Deposition”, Solid State Technology, May 2004, p.53.
88) R. Hillard, M. Benjamin, J. Borland and W. Ye, “Ultra-Shallow Junction Sheet Resistance With A Non-Penetrating Four Point Probe”, Solid State Technology, Aug. 2004, p.47.
89) J. Borland, J. Hatula, T. Tetella, M. Tabat, M. Gwinn and W. Skinner,  “Ge & Ge+B Infusion Doping and Deposition for Ultra-Shallow Junction, Blanket and Localized SiGe or Ge Formation on Cz and SOI Wafers”, the Electrochemical Society Symposium on SiGe Technology, PV 2004-07, p.769.
90) J. Borland, “Alternative USJ Formation & Characterization Methods For 45nm Node Technology”, Ion Implantation Technology, Oct. 2004, Taipei, Taiwan, p. 6.
91) A. Kirkpatrick, J. Borland, J. Hautala & W. Skinner, “Gas Cluster Ion Beam Infusion Doping To Form Ultra-Shallow Junctions And Silicon-Germanium Layers”, presented at IIT-2004, paper A304, Oct. 2004, Taipei, Taiwan.
92) M. Benjamin, R. Hillard and J. Borland, “Ultra-Shallow Junction Sheet Resistance Measurements With A Non-Penetrating Four Point Probe”, Ion Implantation Technology, Oct. 2004, Taipei, Taiwan, p. 351.
93) J. Borland and N. Tokoro, “Consumer Demands Make For A Sizzling Imaging Market In Japan”, Solid State Technology Asia Pacific supplement, Nov. 2004, pS18.
94) J. Borland, M. Tanjyo, M. Nagai, T. Aoyama and D. Jacobson, “Applying Equivalent Scaling To USJ Implantation”, Semiconductor International, Jan. 2005, p.52.
95) J. Hautala, Y. Shao, W. Skinner & J. Borland, “Infusion Processing : An Alternative To Plasma Technology For Semiconductor Device Manufacturing”, the Electrochemical  Society symposium on ULSI Process Integration IV, May 2005, Quebec, Canada, PV 2005-06, p. 118.
96) R. Hillard, M. Benjamin and J. Borland, “Determination of Electrically Acyive Surface Dopant Density in Ultra-Shallow Junctions (USJ) Structures with a Non-Destructive Elastic Material Probe (EM-Probe)”, Ultra Shallow Junction Workshop, June 2005, p. 120.
97) J. Borland, R. Hillard, M. Benjamin, T. Larson and E. Gurer, “Ultra Low Energy (ULE) Implant Dose & Activation Monitoring”, Ultra Shallow Junction Workshop, June 2005, p. 84.
98) ) J. Borland, M. Tanjyo, M. Nagai, T. Aoyama and D. Jacobson, “Applying Implantation Equivalent Scaling To Gate Length Scaling Beyond The 90nm Node”, Ultra Shallow Junction Workshop, June 2005, p. 201.
99) R. Hillard and J. Borland, “USJ Implantation Metrology Issues”, invited paper International Workshop on Junction Technology (IWJT), June 2005, p. 45.
100) J. Borland, E. Gurer, M. Benjamin, W. Skinner, T. Seidel and M. Schumacher, “Dielectrics/Ge-channel Formation: Engineering the Gate Stack”, Solid State Technology, July 2005, p. 45.
101) J. Borland, A. Mineji, W. Krull, M. Tanjo, R. Hillard and T. Walker, ”Using Flash, Laser And SPE Anneals To Optimize 45nm Node P+ USJ With B10 And B18”, Solid State Technology, May 2006, p. 47.
102) J. Borland, S. Shishiguchi, A. Mineji, W. Krull, D. Jacobson, M. Tanjo, W. Lerch, S. Paul, J. Gelpey, S. McCoy, J. Venturini, M. Current, V. Faifer, R. Hillard, M. Benjamin, T. Walker, A. Buczkowski, Z. Li and J. Chen, “45nm Node p+ USJ Formation With High Dopant Activation And Low Damage”, invited paper International Workshop on Junction Technology (IWJT), May 2006, p.4.
103) J. Borland, S. Shishiguchi, A. Mineji, W. Krull, D. Jacobson, M. Tanjo, W. Lerch, S. Paul, J. Gelpey, S. McCoy, J. Venturini, M. Current, V. Faifer, R. Hillard, M. Benjamin, T. Walker, A. Buczkowski, Z. Li and J. Chen, “High Dopant Activation And Low Damage p+ USJ Formation”, Ion Implantation Technology, June 2006 to be published.
104) A. Buczkowski, Z. Li, T. Walker, S. Hummel ad J. Borland, “Non-Contact, Image-Based Photoluminescence Metrology for Ion Implantation and Annealing Process Inspection”, Ion Implantation Technology, June 2006, to be published.
105) J. Gelpey, S. McCoy, D. Camm, W. Lerch, S. Paul, P. Pichler, J. Borland and P. Timans, “Flash Annealing Technology for USJ: Modeling and Metrology”, IEEE/RTP 2006 conference, p. 103.
106) J. Borland, “Process Variability Reduction For Gate Doping And USJs”, Semiconductor International, Dec. 2006, p. 49.
107) R. Hillard, M. Benjamin and J. Borland, “Determination of Implant Activation and Junction Leakage with a Non-penetrating and Non-damaging Elastic Material Probe (EM-Probe)”, to be published at the International Workshop on INSIGHT in Semiconductor Device Fabrication, Metrology and Modeling, May 6-9, 2007 in Napa, CA, p.280.
108) J. Borland, F. Ootsuka, T. Aoyama, T. Onizawa and A. Buczkowski, “Improving Junction Uniformity and Quality with Optimized Diffusion-less Annealing”, the 7th International Workshop on Junction Technology (IWJT 2007), June 8-9, 2007 in Kyoto, Japan, p.69.
109) A. Mineji, J. Borland, S. Shishiguchi, M. Hane, M. Tanjo and T. Nagayama, “Molecular Dopants and High Mass Dopants for HALO and Extension Implantation”, the 7th International Workshop on Junction Technology (IWJT 2007), June 8-9, 2007 in Kyoto, Japan, p.73.
110) J. Borland, “Latest Advances In Implantation, Annealing & Metrology For Gate Poly Doping And Ultra-Shallow Junction Formation For Process Variability Reduction”, the 7th International Workshop on Junction Technology (IWJT 2007), June 8-9, 2007 in Kyoto, Japan, p.39.
111) J. Borland, “32nm Node USJ Implant & Annealing Options”, the IEEE/RTP 2007 conference, Oct. 5, 2007, p.181.
112) J. Borland, “Reducing USJ-Related Device Variability At 32nm”, Solid State Technology, Jan. 2008, p.38.
113) J. Borland, “Implant and Annealing Process Integration Issues to Reduce Device Variability for <10nm p+ & n+ Ultra Shallow Junctions”, IWJT 2008, paper 3.2, p. 68.
114) J. Borland and H. Kiyama, IIT 2008, “Comparison of B, BF2 & B18H22 for Extension and BF2, B18H22 & In HALO Implantation for 32nm Node Using Various Diffusion-less Annealing Techniques”, p.63.
115) J. Borland, Y. Kawasaki, J. Halim and B. Chung, “32nm Node USJ Formation Using Rapid Process Optimization Metrology”, Solid State Technology, July 2008, p. 38.
116) M. Current and J. Borland, “New Metrologies For Annealing of USJs and Thin Films”, IEEE-RTP 2008 meeting, Oct. 2008, p.43.
117) M. Tanjyo, N. Hamamoto, T. Nagayama, S. Umisedo, Y. Koga, N. Maehara, H. Une, T. Matsumoto, N. Nagai and J. Borland, “Cluster Ion Implantation System: Claris For Beyond 45nm Device Fabrication”, Semicon/China 2009, March 2009.
118) J. Borland, M. Tanjyo, T. Nagayama and N. Hamamoto, “High Tilt P+ & N+ Molecularf Implantation For 3-D Structures: Retained Chemical Dose Versus Elecgtrical Activation Limited Conformal Doping”, Insights 2009 meeting, April 2009, p.352.
119) J. Borland, Z. Wan, S. Muthukrishnan, J. Zelenko, I. Mirshad, W. Johnson and T. Buyuklimanli, “22nm Node P+USJ Using Xe-PAI & Laser Annealing”, Insights 2009 meeting, April 2009, p.25.
120) J. Borland, S. Felch, Z. Wan, M. Tanjyo and T. Buyuklimanli, “Thermal Processing Issues For 22nm Node Junction Scaling”, Solid State Technology, August 2009, p. 14.
121) J. Borland, M. Tanjyo, N. Hamamoto, T. Nagayama, S. Muthukrishnan, J. Zelenko, I. Mirshad, W. Johnson and T. Buyuklimanli, “22nm Node p+ Junction Scaling Using B36H44 And Laser Annealing With or W/O PAI”, IEEE-RTP 2009 meeting, p.49.
122) J. Borland, M. Tanjyo, N. Hamamoto, T. Nagayama, S. Muthukrishnan, J. Zelenko, I. Mirshad, W. Johnson, T. Buyuklimanli, H. Itokawa, I. Mizushima and K. Suguro, “22nm Node n+SiC Stressor Using Deep PAI+C7H7+P4 With Laser Annealing”, IEEE-RTP 2009 meeting, p.59.
123) J. Borland, J. Marino, M. Current and B. Darby, “22nm Node p+ USJ Formation Using PAI & HALO Implantation With Laser Annealing”, IIT-2010, to be published.
124) J. Borland, S. Shishiguchi, N. Matsuzaka, M. Hane, M. Tanjyo, P. Oesterlin and J. Mayer, “Comparison of Solid Phase Epi (SPE) Non-Melt to Liquid Phase Epi (LPE) Melt Laser Annealing For 22nm Node n+ USJ Formation”, IEEE-RTP 2010 meeting, p. 18.
125) J. Borland, M. Tallian, D. Kosztka, A. Pap, K. Mocsar, A. Somogyi, G. Nadudvari, L. Jastrzebski and T. Pavelica, “22nm node p+ USJ Defect Analysis With Various PAI and HALO Structures Using Laser Annealing, IEEE-RTP 2010 meeting, p. 158.
126) J. Borland and T. Buyuklimanli, “Influence of Surface Passivation on B, B18H22 and B36H44 Retained Dose for USJ”, International Workshop on Junction Technology 2011, paper S7-3.
127) J. Borland, M. Tanjyo, S. Sakai, T. Nagayama, H. Kiyama and K. Suguro, “Comparison of BF2, In, Ga, C+Ga & In+BF2 Dopant for 22nm Node Bulk & PD-SOI HALO Implantation or Ground Plane Back-Gate Doping for FD-SOI CMOS Technologies”, International Workshop on Junction Technology 2012, paper S1-02, p.38.
128) B. Wo, Y. Matsunaga, S. Aid, S. Matsumoto, J. Borland and M. Tanjyo, “Characteristics of BF2, Ga and In Implanted Si after FLA and RTA Annealing”, International Implant Technology Conference 2012, Valladolid, Spain, paper P1-25.
129) J. Borland, V. Moroz, J. Huang, J. Chen, YJ Lee, P. Oesterlin, P. Venema, H. Geerman, P. Zhao and L. Wang, “Selective and Homo Emitter Junction Formation Using Precise Dopant Concentration Control by Ion Implantation and Microwave, Laser or Furnace Annealing Techniques”, IEEE Photovoltaic Specialists conference 2012, paper 626.
130) J. Borland, J. Chen, P. Oesterlin, P. Venema, H. Geerman, YJ Lee, P. Zhao, L. Wang, B. Xu and S. Qin, “Comparison of POCL3 & BBR3 Furnace Diffusion Dopant Sources to Phosphorus & Boron Implant and Plasma Dopant Sources for Selective Emitter Formation Using Localized LAser Melt (LLM) Annealing Either Before or After SiN/ARC”, European Photovoltaic Solar Energy conference 2012, paper 2AV.6.32.
131) J. Borland, S. Qin, P. Oesterlin, K. Huet, W. Johnson, L. Klein, G. Goodman, A. Wan, S. Novak, T. Murray, A. Joshi and S. Prussin, “High Mobility Ge-channel Formation By Localized/Selective Liquid Phase Epitaxy (LPE) Using Ge+B Plasma Ion Implantation and Laser Melt Annealing”, International Workshop on Junction Technology 2013, paper S4-4, p.49.
132) Y. Matsunaga, S. Aid, S. Matsumoto, J. Borland and M. Tanjyo, “Characterization of BF2, Ga and In Dopants for HALO Implantation”, International Workshop on Junction Technology 2013, paper S6-3, p.74.
133) J. Borland and P. Konkola, “Implant Dopant Activation Comparison Between Silicon and Germanium”, International Implant Technology Conference 2014, Portland, OR, June 30, 2014, page 45.
134) J. Borland, M.Sugitani, P. Oesterlin, W. Johnson, T. Buyuklimanli, R. Hengstebeck, E. Kennon, K. Jones and A. Joshi, “Liquid Phase Epitaxy (LPE) Formation of Localized High Quality and Mobility Ge & SiGe by High Dose Ge-Implantation with Laser Melt Annealing for 10nm and 7nm Node CMOS Technology”, Oct 2014 ECS meeting 6th International SiGe, Ge & Related Compounds, paper P7-1771, page 127, ECStransactions, vol.64, no.6, 2014.
135) J. Borland, J. Herman, S. Novak, H. Onoda, Y. Nakashima, K. Huet, W. johnson and A. Joshi, “P, Sb and Sn Ion Implantation with Laser Melt-LPC (Liquid Phase Crystallization) for High Activation n+ Ultra Shallow Junction in Ge Epilayer and Surface Strain-Ge Formation for Mobility Enhancement”, International Workshop on Junction Technology 2015, paper S2-1, page12.
136) J. Borland, “Smartphone ICs Driving Technology to 3-D Stacked Devices/Chips, 3-D Doped FinFET Transistors and High Mobility Channel Materials From 20/22nm Production to 5/7nm Exploratory Research”, Oct 2015 ECS meeting Symposium on ULSI Process Integration 9, paper G04-1073.
137) J. Borland, “High Electron and Hole Mobility by Tensile and Compressive Strain Formation Using Ion Implantation and Advanced Annealing of Group IV Materials (Si, SiGe & Ge)”, Oct 2016 ECS Meeting symposium on High Purity and High Mobility Semiconductors 14.
138) J. Borland, M. Sugitani, S. Chaung, YJ Lee, K. Huet, A. Joshi, A. Wan, L Wong, P. Horvath and A. Finley, “Surface Strained Ge-Cz Wafers by Sn-implantation for High Electron and Hole Mobility”, International Implant Technology Conference 2016, Tainan, Taiwan.
139) J. Borland, M. Sugitani, J. Herman, K. Huet, W. Johnson, L. Yu and A. Joshi, “High & Low Dose USJ Formation Into Ge-epi on Si Wafers: Dopant Activation, Damage Recovery and Mobility Effects”, International Implant Technology Confernce 2016, Tainan, Taiwan.

140) J. Borland, “Smartphone Market Driving 7nm & 5nm Node 3-D Devices and Stacked Devices”, 7th International Symposium on Advanced Science and Technology of Silicon (JSPS Si Sym), Nov 21-25, 2016 Kona, Hawaii, paper N-1, p. 211.

146) J. Borland, “Be Proactive Not Reactive to the Next Island Blackout: A Case Study for Achieving 100% Renewable Energy From the Sun + Multiple Storage For Hawaii Residences with <3 Years Payback & Off-Grid Operation”, Wiliki-o-Hawaii, vol.53, no.10, Dec 2017.