John Borland`s Biography

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               John Ogawa Borland received his B.S. and M.S. degrees in Material Science and Engineering from the Massachusetts Institute of Technology (MIT) in Cambridge, MA. He completed his BS thesis research on InP Liquid Phase Epitaxial (LPE) crystal growth at Hughes Malibu Research Labs in 1980 and his MS thesis research on InP Molecular Beam Epitaxial (MBE) crystal growth at Nippon Telephone and Telegraph (NTT) Labs in Musashino, Tokyo, Japan in 1981. He is a senior member of IEEE and the IEEE Hawaii section chair, a member of the Electrochemical Society (ECS) and Materials Research Society. He is co-organizer for the Symposium on ULSI Process Integration IV (2005) and was on the organizing committee for the 2001 & 2003 symposiums, Semiconductor Silicon (1994 & 1998) and Chemical Vapor Deposition X, XI & XII (1987, 1989, & 1991). He also is advisory committee co-chair for the IEEE International Workshop on Junction Technology (2008, 2010, 2011, 2012, 2013 and 2014). He has published over 135 technical and invited papers around the world and has been awarded 6 patents all in the areas of advanced semiconductor device manufacturing techniques. He is also on the Editorial Advisory Board of Solid State Technology magazine.
            He was Director of Operations of APIC’s subsidiary Advanced Integrated Photonics which is their Silicon Photonics Foundry Fab in Honolulu, Hawaii from April 2013 to Aug 2014. In June 2003 he founded and is president of JOB Technologies a strategic marketing, sales and technology consulting company providing service to the semiconductor device manufacturing and equipment companies in the area of 14nm down to 7nm node front end of line process development focusing on Ge high mobility material and technology for CMOS. Through his consulting activities he is involved in: 1) strategic marketing and sales of front end of line equipment, 2) creating a new market for and inventing a new 3-D back-side illumination CMOS & CCD imagers using transparent substrates and super MeV for wireless camera applications, 3) high-k gate dielectric process development, 4) developing new metrologies to accurately characterize ultra-shallow junctions, 5) new zero diffusion processing techniques to achieve USJ with semiconductor IC and equipment companies and 6) creating a new market for and inventing localized and blanket Ge processing for sub-10nm node. From July 1998 to May 2003 he was Director of Advanced Business Development at Varian Semiconductor Equipment Associates. While at VSEA, he invented the high tilt high current PoGI process for process simplification and improved device lateral channel and source drain engineering. He also led the revived interest in low temperature diffusion-less activation by solid phase epitaxy (SPE) and its inclusion in the 2003 ITRS roadmap. From Nov. 1992 to July 1998 he was Vice President of Strategic Technology at Genus before they were acquired by Varian and invented the MeV BILLI structure for CMOS epi replacement, process simplification and improved latch-up performance. From Sept. 1983 to Nov. 1992 he was at Applied Materials and pioneering advanced silicon epitaxial and polysilicon/amorphous deposition techniques and equipment designs for blanket epi and polysilicon. He also patented some of his work on selective epi (SEG) and selective poly through surface interface cleaning techniques. This led to the successful implementation of SEG for local strap and elevated source drain by a major DRAM manufacturing company in 1987. Also, a variation to his epitaxial lateral overgrowth (ELO) for SOI is used today for epitaxial bonded SOI wafer manufacturing. From Aug. 1981 to Sept. 1983 he was at National Semiconductor Corp. developing the VHSIC-CMOS front end processing including bulk and epi wafer intrinsic gettering for improved gate oxide integrity and yield as well as substrate and CMOS well engineering for improved latch-up immunity.
    

  

 

 

 

 

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